The design of future power electronics systems will continue to advance to achieve the highest levels of performance and power density. In response to this trend, Infineon is introducing a new line of source bottom-mount power MOSFETs in a 3.3 x 3.3 mm2 PQFN package covering the voltage range 25-150 V and available in bottom-sided-cooling (BSC) and double-sided-cooling (DSC) configurations. The new product family offers important performance improvements at the semiconductor device level, providing an attractive solution for DC-DC power conversion and opening up new possibilities for system innovation in server, communication, OR-ing, battery protection, power tool, and charger applications.
This new product family uses Infineon's latest MOSFET product technology and leading-edge packaging technology to take system performance to a new level. Inside the Source down (SD) package, the source contacts of the MOSFET wafer are flipped and o riented towards the bottom side of the package and then soldered to the PCB. In addition, the package has an improved drain copper clip design inside the top of the chip, achieving a market-leading chip/package area ratio. As system sizes continue to get smaller, the key factors of reduced power loss and improved heat dissipation become critical. Infineon's new product family offers a significant 25% reduction in on-resistance (RDS(on)) compared to devices in the current market-leading PQFN 3.3 x 3.3 mm2 drain-bottom package. Infineon's double-sided heat sink, PQFN package, OptiMOS source-bottom power MOSFETs provide an enhanced thermal interface to transfer power losses from the switching device to the heat sink. The double-sided heat sink structure enables the most direct way to connect the power switch to the heat sink, with a three-fold increase in power consumption capability compared to bottom-sink, source-bottom power MOSFETs. This new product family offers two different pin arrangements, providing great flexibility for PCB routing. The pin arrangement with a traditional standard gate layout allows for quick and easy modification of existing drain bottom designs, while the pin arrangement with a centered gate layout offers new possibilities for paralleling multiple devices and minimizing the alignment distance between the driver chip and the gate. The new generation of 25-150 V OptiMOS source-bottom power MOSFETs in PQFN 3.3 x 3.3 mm2 packages offer excellent continuous current capability up to 298A for maximum system performance.
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