Intel Breaks Through Interconnect Bottlenecks with PowerVia Back Side Power Technology to Meet New Era of Computing Demand
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Update time : 2023-06-08 10:55:29
Intel is the first to implement backside power technology on a product-level chip, enabling over 90 percent cell utilization while also demonstrating industry-leading performance in other dimensions.
Intel announced the industry's first implementation of backside power delivery technology on a product-level test chip to meet the performance demands of the next era of computing. As Intel's industry-leading backside power solution, PowerVia will be available on the Intel 20A process node in the first half of 2024. By moving power lines to the back of the wafer, PowerVia addresses the growing interconnect bottleneck in chip unit area miniaturization. PowerVia is an important milestone for both Intel's aggressive 'five process nodes in four years' plan and its commitment to integrate one trillion transistors in a single package by 2030," said Ben Sell, Intel's vice president of technology development. PowerVia is an important milestone for both of these goals. By using pilot production process nodes and their test chips, Intel has reduced the risk of using backside power for advanced process nodes, enabling us to bring backside power technology to market one process node ahead of our competitors." The development of the test chip, codenamed "Blue Sky Creek," has helped Intel refine its PowerSide technology. Product testing has helped Intel refine its PowerVia backside power technology, which is expected to launch with the Intel 20A process node in 2024 and is the industry's first backside power on a chip, solving a decades-old interconnect bottleneck problem. Intel is separating the development of PowerVia technology and transistors to ensure that PowerVia can be properly used in the production of Intel 20A and Intel 18A process chips. Prior to integration with the RibbonFET transistor, which will also be introduced with the Intel 20A process node, PowerVia was tested on its internal test node to continuously debug and ensure it functions well. By adopting and testing PowerVia on test chips, Intel confirmed that the technology can indeed significantly improve the efficiency of chip usage, cell utilization of more than 90%, and help achieve significant shrinkage of transistors, allowing chip design companies to enhance product performance and energy efficiency.
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