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GUC Officially Ships UCIe 32G IP Based on TSMC 3nm and CoWoS Technology

Update time : 2024-01-16 16:32:50

Global Unichip Corp.（GUC）, a leading supplier of advanced special application ICs (ASICs), today announced that it has successfully prototyped 32Gbps-per-channel Universal Chiplet Interconnect Express™ (UCIe™) physical layer IP, the fastest UCIe available, which will be utilized in AI/high performance computing (HPC)/xPU/networking applications. High Performance Computing (HPC)/xPU/networking applications. UCIe 32G small-chip interface offers industry-leading bandwidth density of up to 10 Tbps per 1mm die edge (5 Tbps/mm full duplex). The chip utilizes TSMC's N3P silicon wafer process and CoWoS® advanced packaging technology.
GUC has been developing a series of small-chip interconnect IPs (GLink-2.5D) for TSMC's N7, N5, and N3 process nodes in recent years. The GLink-2.5D IPs have been flow-proven to operate robustly at up to 17.2 Gbps with a raw BER of <1E-20. In addition, with the built-in CRC checksum design and retransmission buffer, they can achieve a FIT of well below 1, thus meeting the most stringent reliability requirements. GLink-2.5D supports all TSMC 2.5D technologies (CoWoS-S/R/L, InFO_oS).
The UCIe Consortium has a vision of interoperability for small chip interfaces. GUC has already developed a number of GLink-2.5D IP products that have been validated in prototypes, and we are able to fully utilize our strengths in this area when introducing UCIe, thus minimizing the risk of moving to UCIe with the best performance parameters. GUC has also developed bridges for AXI, CXS and CHI buses using the UCIe Streaming Protocol. These bridges are optimized for high traffic density, low power consumption, low data transfer latency, and efficient end-to-end process control for a smooth transition from single-chip NoCs to small-chip architectures; they also support Dynamic Voltage Frequency Scaling (DVFS), which allows the voltage and bus frequency to be changed at any time according to the performance requirements without interrupting the data flow.
GUC' UCIe IP supports the UCIe-1.1 Preventive Monitoring function, which incorporates proteanTecs' I/O signal quality monitor and has already been tested in the GLink-2.5D series. The monitoring function continuously monitors the signal quality in task mode during data transmission without retraining or any other interruption of the data transmission. Each signal channel is continuously monitored and reported separately, and power and signal integrity events are also detected. In addition, the monitoring feature preemptively identifies defects such as bumps and transmission lines that could cause the interface to fail, and the repair algorithm then replaces channels that are near I/O thresholds with backup channels to prevent system failure and extend the life of the chip.
We are honored to announce the world's first UCIe IP supporting 32 Gbps," said Aditya Raina, marketing director of GUC. "We have built a complete portfolio of 2.5D/3D small-chip, wafer-proven IPs using TSMC's 7nm, 5nm and 3nm technologies. GUC will combine its design expertise, package design, electrical and thermal simulation, as well as DFT and production test capabilities for TSMC's 3DFabric products, including CoWoS, InFO and SoIC, to provide customers with a robust and comprehensive solution to shorten their design cycle and fast-track the launch of products such as Artificial Intelligence (AI)/high performance computing (HPC)/xPU/networking. /Networking, etc."
We are committed to delivering the fastest and lowest power 2.5D/3D small chip and HBM interface IP," said Igor Elkanovich, GUC. Both 2.5D and 3D packages are now trending towards HBM3/4, Glink-2.5D/UCIe and Glink-3D interfaces, which will enable the development of highly modular and far larger mask scale new generation processors in the future. This will enable the development of a new generation of processors that are highly modular and much larger than the size of the photomask."

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