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Infineon's QDPAK and DDPAK Top Cooled Packages for High Power Applications Registered to JEDEC Standards

Update time : 2023-04-15 11:03:00

Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY) announces that its QDPAK and DDPAK top cooling (TSC) packages for high voltage MOSFETs have been successfully registered to the JEDEC standard. This initiative not only further reinforces Infineon's goal of extending this standard package design and form factor TSC package to a wide range of new designs, but also gives OEMs more flexibility and advantages to help them create differentiated products in the market and increase power density to higher levels to support a variety of applications.

As a solution provider, Infineon continues to make an impact on the semiconductor industry through innovative packaging technologies and processes," said Ralf Otremba, Chief Engineer, High Voltage Packaging, Infineon Technologies. Our advanced top-cooled packages bring significant advantages at the device and system level to meet the challenging requirements of cutting-edge high power designs. The standardization of package form factors ensures pin compatibility across vendor designs - one of the key design considerations faced by OEMs in high voltage applications - thereby eliminating the need for OEMs to expend effort in this area."
The successful registration of the QDPAK and DDPAK surface mount (SMD) TSC package designs marks a new era in package form factor and will drive wider adoption of TSC technology to replace TO247 and TO220. The new JEDEC-registered package series will be an important enabler for the transition to top-cooled designs in next-generation platforms for high voltage industrial and automotive applications.
To assist customers in the design transition of TO220 and TO247 THD devices, Infineon is offering QDPAK and DDPAK SMD devices that offer the same thermal capability and better electrical performance. The QDPAK and DDPAK SMD TSC packages for HV and LV devices are available in a standard 2.3 mm height, allowing developers to design complete applications such as OBC and DC-DC conversion using all SMD TSC devices of the same height. This package is not only better for the design but also reduces cooling system costs compared to existing solutions that must use 3D cooling systems.
In addition, the TSC package reduces thermal resistance by up to 35% compared to standard bottom cooling (BSC), and the TSC package leverages the benefits of both sides of the PCB to provide better board space utilization and at least twice the power density. The thermal decoupling of the substrate also improves the thermal management of the package as the package pins have a much higher thermal resistance than the exposed top of the package. The improved thermal performance eliminates the need for stacking different boards. A single FR4 is sufficient for all components, eliminating the need to combine FR4 and IMS, and requiring fewer connectors. These features contribute to the overall bill of materials (BOM), which ultimately reduces overall system cost.
In addition to improved heat dissipation and power capability, TSC technology also provides better power loop design because the driver can be configured very close to the power switch, making it more stable. The low stray inductance of the driver switching circuit reduces circuit parasitic effects, resulting in less gate oscillation, higher performance, and less risk of failure.

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