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The development of 3D packaging technology will be the future of semiconductors

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Update time : 2022-09-12 14:25:38
        The first CPU 4004 released by Intel in 1971 had about 2,300 internal transistors. Five years later, Intel's Ponte Vecchio processor packed 47 chiplets with more than 100 billion transistors into one processor, using 2.5 in the process. 3D and 3D technology. On January 5, 2022, AMD released the first 3D stacked desktop processor Ryzen 7 5800X3D. Thanks to 3D chip stacking, the average performance of Zen 3 has increased by 19% compared to Zen 2. On March 4, 2022, AI chip company Graphcore's Bow IPU chip uses 3D stacking technology to increase AI speed by 40%. On March 9, 2022, Apple released the M1 Ultra, the highest-end processor chip for computers, connecting 2 chips arranged horizontally to each other and equipped with 114 billion transistors.
 
 
        Various examples show that 2.5D/3D packaging technology is becoming an important means of improving chip performance. The importance of 3D stacking technology is increasing by enabling the highest levels of silicon integration and area efficiency at the lowest cost. Brand new applications are also emerging, and 3D stacking technology has emerged as a lucrative solution to meet the performance requirements of applications such as artificial intelligence, machine learning and data centers.
        Today, 3D packaging has become one of the key technologies for the industry's top chip companies such as Intel, AMD, NVIDIA, and Apple. Although heterogeneous packaging represented by 3D IC has become a key development direction in the future, the implementation of new technologies has to face many difficult problems. Compared with traditional packaging technology, 2.5D/3D IC heterogeneous packaging is not only an innovation in packaging factory technology, but also brings challenges to the original design process, design tools, and simulation tools.
        Furthermore, to manufacture 3D chips, new technological innovations in the field of manufacturing equipment and raw materials are required. One of the key important materials is the ABF carrier for the connection of multiple chips. ABF carrier board is a kind of IC carrier board. ABF carrier board can be used as IC with thin lines and suitable for high pin count and high message transmission. It has high computing performance and is mainly used for CPU, GPU, FPGA, ASIC, etc. Computing performance chips. In recent years, the development of technologies such as Chiplets has increased the demand for ABF substrates, and there are also issues such as how to increase connection speed, improve heat dissipation, and reduce costs. At present, major ABF carrier board suppliers including Xinxing, Jingshuo, Nandian, Ibiden, Shinko, AT&S, etc. have all expanded their production to a certain extent.
        At the same time, the collaboration between EDA manufacturers and foundries and packaging houses is becoming more and more important. In this regard, Siemens EDA has actively cooperated with TSMC, Samsung and ASE to provide them with ecological support.
Among them, as early as 2020, Siemens EDA won the annual OIP Partner Award for TSMC's "Joint Development of 3DIC Design Productivity Solutions". Key milestones reached. Furthermore, Siemens EDA's high-density advanced packaging solutions have been certified by Samsung Foundry's latest packaging process. Siemens EDA also leverages its XpeditionSubstrate Integrator software and Calibre® 3DSTACK platform with ASE to launch a new generation of supporting technologies for high-density advanced packaging design, according to Dr. Hong Zhibin, Vice President of ASE Group: "The cooperation between the two parties enables customers to reduce 2.5D/3D IC and FOCoS package planning and verification cycles can reduce design development time by approximately 30% to 50% in each design cycle.
All in all, with the gradual improvement of the entire industry chain and the continuous introduction of new supporting technologies in various fields, such as 2.5D and 3D packaging technology, it will become the mainstay of the next chip performance improvement process, and it will also be the future of the semiconductor industry.


 
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