Processor: Equipped with Arm® Cortex®-M0+ 32-bit core integrated with Memory Protection Unit (MPU), up to 32 MHz main frequency, achieving 0.95 DMIPS/MHz performance.
Low-Power Modes: Supports multiple low-power modes for energy efficiency optimization:
Flash Memory: 192 KB, supporting Dual Bank read/write with ECC error correction, secure boot, and code encryption.
SRAM: 20 KB, enabling zero-wait-state access during operation.
EEPROM: 6 KB data EEPROM with ECC for non-volatile data storage.
Backup Registers: 20 bytes, retaining data in Standby mode.
ADC: 12-bit analog-to-digital converter, up to 1.14 Msps sampling rate, supporting 16 channels (including 3 internal channels like temperature sensor and voltage reference). Hardware oversampling can enhance precision to 16 bits.
DAC: 2-channel 12-bit digital-to-analog converter with output buffer, supporting noise and triangular wave generation.
Comparator: 2 ultra-low-power comparators, supporting window mode and wake-up function, input voltage range 0 to VDD.
Temperature Sensor: Integrated temperature sensor with factory-calibrated data stored in system memory, accuracy up to ±2°C.
LPUART: Low-power UART supporting wake-up from Stop mode, up to 46 Kbaud baud rate.
SPI/I2S: 6 SPI interfaces (up to 16 Mbit/s), 1 I2S interface for audio communication.
CAN: Not explicitly mentioned in the document, but a typical function of the STM32L073 series (model-specific confirmation required).
Power Range: Wide voltage supply 1.65 V to 3.6 V, supporting Brown-out Reset (BOR) and Programmable Voltage Detector (PVD).
Clock Sources:
External Clocks: High-speed external crystal (HSE, 1-25 MHz) and low-speed external crystal (LSE, 32.768 kHz).
Internal Clocks: HSI (16 MHz), LSI (37 kHz), MSI (65 kHz to 4.2 MHz, adjustable).

| Type | Description |
|---|---|
| Category | Integrated Circuits (ICs) Embedded Microcontrollers |
| Mfr | STMicroelectronics |
| Series | STM32L0 |
| Packaging | Tray |
| Part Status | Active |
| DigiKey Programmable | Not Verified |
| Core Processor | ARM® Cortex®-M0+ |
| Core Size | 32-Bit Single-Core |
| Speed | 32MHz |
| Connectivity | I2C, IrDA, LINbus, SPI, UART/USART, USB |
| Peripherals | Brown-out Detect/Reset, DMA, I2S, LCD, POR, PWM, WDT |
| Number of I/O | 84 |
| Program Memory Size | 192KB (192K x 8) |
| Program Memory Type | FLASH |
| EEPROM Size | 6K x 8 |
| RAM Size | 20K x 8 |
| Voltage - Supply (Vcc/Vdd) | 1.8V ~ 3.6V |
| Data Converters | A/D 16x12b; D/A 2x12b |
| Oscillator Type | Internal |
| Operating Temperature | -40°C ~ 85°C (TA) |
| Mounting Type | Surface Mount |
| Supplier Device Package | 100-LQFP (14x14) |
| Package / Case | 100-LQFP |
| Base Product Number | STM32L073 |

| Pin Name | Pin Number | Function Description |
|---|---|---|
| VDD | 28, 73, 100 | Main power input (1.65–3.6 V), powers digital logic and internal regulators, needs to be grounded via decoupling capacitors. |
| VSS | 27, 74, 99 | Digital ground, provides system reference ground. |
| VDDA | 22 | Analog power input (1.65–3.6 V), powers analog peripherals like ADC, DAC, etc., needs to be connected to VDD. |
| VSSA | 19 | Analog ground, independent of digital ground to ensure analog circuit stability. |
| VDD_USB | 75 | Dedicated power for USB module (≥3.0 V to ensure normal USB communication), can be connected to VDD or VSS when not in use. |
| VLCD | 6 | Power output for LCD controller, with built - in boost converter, supports LCD voltage driving independent of VDD. |
| Pin Number | Function Description (Default / Alternate Function) |
|---|---|
| PA0 | ADC_IN0, TIM2_CH1, TSC_G1_IO1 (Touch Sensing), USART2_CTS |
| PA1 | ADC_IN1, TIM2_CH2, USART2_RTS/DE, EVENTOUT |
| PA2 | ADC_IN2, TIM21_CH1, USART2_TX, LPUART1_TX, COMP2_OUT |
| PA3 | ADC_IN3, TIM21_CH2, USART2_RX, LPUART1_RX |
| PA4 | ADC_IN4, DAC_OUT1, SPI1_NSS, TSC_G2_IO1 |
| PA5 | ADC_IN5, DAC_OUT2, SPI1_SCK, TIM2_ETR |
| PA6 | ADC_IN6, SPI1_MISO, TIM3_CH1, EVENTOUT, COMP1_OUT |
| PA7 | ADC_IN7, SPI1_MOSI, TIM3_CH2, EVENTOUT, COMP2_OUT |
| PA8 | MCO (Clock Output), LCD_COM0, USART1_CK, I2C3_SCL |
| PA9 | USART1_TX, I2C1_SCL, TSC_G4_IO1, LCD_COM1 |
| PA10 | USART1_RX, I2C1_SDA, TSC_G4_IO2, LCD_COM2 |
| PA11 | USB_DM, SPI1_MISO, USART1_CTS, COMP1_OUT |
| PA12 | USB_DP, SPI1_MOSI, USART1_RTS/DE, COMP2_OUT |
| PA13 | SWDIO (Debug Interface), LPUART1_RX |
| PA14 | SWCLK (Debug Clock), USART2_TX, LPUART1_TX |
| PA15 | SPI1_NSS, TIM2_ETR, USART2_RX, LCD_SEG17 |
| Pin Number | Default Function / Alternate Functions (AF) |
Key Characteristics |
|---|---|---|
| PB0 | ADC_IN8, VREF_OUT, LCD_SEG5, TIM3_CH3, TSC_G3_IO2, I2C3_SDA | 5V tolerant (FT), supports ADC input, internal reference voltage output, LCD segment, timer channel, touch sensing, and I2C3 data pin. |
| PB1 | ADC_IN9, VREF_OUT, LCD_SEG6, TIM3_CH4, TSC_G3_IO3, LPUART1_RTS/DE | 5V tolerant (FT), supports ADC input, reference voltage output, LCD segment, timer channel, touch sensing, and low-power UART hardware flow control. |
| PB2 | LCD_VLCD2, LPTIM1_OUT, TSC_G3_IO4, I2C3_SMBA | 5V tolerant (FT), LCD bias output, low-power timer output, touch sensing, and I2C3 SMBus management bus; supports power management protocols. |
| PB3 | TIM2_CH2, SPI1_SCK, USART1_RTS/DE, USART5_TX, TSC_G5_IO1 | 5V tolerant (FT), timer channel, SPI1 clock, USART flow control, USART5 transmission, and touch sensing; supports high-speed serial communication. |
| PB4 | TIM22_CH1, SPI1_MISO, LCD_SEG8, TIM3_CH1, TSC_G5_IO2, USART1_CTS | 5V tolerant (FTf), timer channel, SPI1 slave data input, LCD segment, touch sensing, and USART1 flow control; supports multi-timer synchronization. |
| PB5 | TIM22_CH2, SPI1_MOSI, LCD_SEG9, LPTIM1_IN1, I2C1_SMBA, USART1_CK | 5V tolerant (FT), timer channel, SPI1 master data output, LCD segment, low-power timer input, and I2C1 SMBus; supports synchronous communication. |
| PB6 | USART1_TX, I2C1_SCL, LPTIM1_ETR, TSC_G5_IO3 | 5V tolerant (FTf), USART1 transmission, I2C1 clock, low-power timer external trigger, and touch sensing; supports low-power communication wake-up. |
| PB7 | USART1_RX, I2C1_SDA, LPTIM1_IN2, TSC_G5_IO4, PVD_IN | 5V tolerant (FTf), USART1 reception, I2C1 data, low-power timer input, touch sensing, and voltage detection input; supports power monitoring. |
| PB8 | LCD_SEG16, TSC_SYNC, I2C1_SCL (multiplexed) | 5V tolerant (FTf), LCD segment output, touch sensing sync signal, and I2C1 clock; suitable for HMI and touch control integration. |
| PB9 | LCD_COM3, EVENTOUT, I2C1_SDA (multiplexed), SPI2_NSS/I2S2_WS | 5V tolerant (FTf), LCD common control, event output, I2C1 data, and SPI2/I2S slave select; supports multi-protocol multiplexing. |
| PB10 | LCD_SEG10, TIM2_CH3, LPUART1_TX, SPI2_SCK/I2S2_CK, I2C2_SCL, TSC_G6_IO1 | 5V tolerant (FT), LCD segment, timer channel, low-power UART transmission, SPI2/I2S clock, I2C2 clock, and touch sensing; supports multi-function multiplexing. |
| PB11 | LCD_SEG11, TIM2_CH4, LPUART1_RX, SPI2_MISO/I2S2_MCK, I2C2_SDA | 5V tolerant (FT), LCD segment, timer channel, low-power UART reception, SPI2/I2S data input, and I2C2 data; suitable for complex peripheral setups. |
| PB12 | SPI2_NSS/I2S2_WS, LCD_SEG12, LPUART1_RTS/DE, TSC_G6_IO2, I2C2_SMBA | 5V tolerant (FT), SPI2/I2S slave select, LCD segment, low-power UART flow control, touch sensing, and I2C2 SMBus; supports bus management. |
| PB13 | SPI2_SCK/I2S2_CK, LCD_SEG13, MCO, LPUART1_CTS, TSC_G6_IO3, TIM21_CH1 | 5V tolerant (FTf), SPI2/I2S clock, LCD segment, clock output, low-power UART flow control, and timer channel; supports high-speed clock output. |
| PB14 | SPI2_MISO/I2S2_MCK, LCD_SEG14, RTC_OUT, TSC_G6_IO4, LPUART1_RTS/DE, I2C2_SDA, TIM21_CH2 | 5V tolerant (FTf), SPI2/I2S data input, LCD segment, RTC output, touch sensing, low-power UART control, and timer channel; supports real-time clock and communication integration. |
| PB15 | SPI2_MOSI/I2S2_SD, LCD_SEG15, RTC_REFIN | 5V tolerant (FT), SPI2/I2S data output, LCD segment, and RTC reference input; suitable for audio or real-time data transmission applications. |
| Pin Number | Function Description | Key Characteristics |
|---|---|---|
| PA11 | USB_DM | USB data minus line, supports full-speed (12 Mbit/s) communication with built-in DP pull-up resistors; compatible with USB 2.0 protocol. |
| PA12 | USB_DP | USB data plus line, supports battery charging detection (BC1.2 protocol); works with PA11 for USB communication. |
| VDD_USB | 75 | Independent power for USB module (≥3.0V for normal operation); can be grounded or connected to VDD when unused. |
| Pin Number | Function Description | Key Characteristics |
|---|---|---|
| PA2/PA3 | USART2_TX/USART2_RX | Support hardware flow control (CTS/RTS); can be multiplexed as LPUART1_TX/RX (low-power UART, supports 9600 baud with only LSE clock). |
| PA9/PA10 | USART1_TX/USART1_RX | Support synchronous mode (CK pin), IrDA, LIN master/slave modes; compatible with ISO 7816 smart card interface. |
| PB6/PB7 | USART1_TX/USART1_RX | Support asynchronous communication, can wake up from Stop mode (baud rate ≤42 Kbaud); suitable for low-power communication scenarios. |
| PB10/PB11 | LPUART1_TX/LPUART1_RX | Low-power UART, supports half-duplex single-wire communication and auto-baud rate detection; wake-up current as low as 0.5 µA. |
| Pin Number | Function Description | Key Characteristics |
|---|---|---|
| PA4/PA5/PA6/PA7 | SPI1_NSS/SCK/MISO/MOSI | SPI1 master/slave interface, up to 16 Mbit/s, supports CRC hardware check and SD card protocol. |
| PB3/PB5/PB13/PB15 | SPI2_SCK/MOSI/SCK/MOSI | SPI2 interface, can be multiplexed as I2S audio interface; supports 16-/32-bit audio data transmission. |
| PA9/PA10 | I2C1_SCL/SDA | I2C1 master/slave interface, supports standard mode (100 kbit/s), fast mode (400 kbit/s), and SMBus/PMBus protocols. |
| PB10/PB11 | I2C2_SCL/SDA | I2C2 interface, supports multi-slave addressing and wake-up from Stop mode via address matching. |
| PB0/PB2 | I2C3_SDA/SMBA | I2C3 interface, supports SMBus management bus (SMBA) for power management and sensor communication. |
| Pin Number | Function Description | Key Characteristics |
|---|---|---|
| PA0/PA1 | TIM2_CH1/CH2 | 16-bit timer channels, support PWM output (16-bit resolution), input capture (frequency/pulse width measurement). |
| PA6/PA7 | TIM3_CH1/CH2 | 4-channel timers, support complementary PWM output (with dead-time control); can drive motors or power devices. |
| PB3/PB10 | TIM2_CH2/CH3 | Timer channels, support external trigger (ETR) and encoder interface; suitable for motor control and position detection. |
| PC6/PC7 | TIM22_CH1/CH2 | 16-bit timers, support independent clock sources (e.g., LSE); suitable for low-power timing tasks. |
| Pin Number | Function Description | Key Characteristics |
|---|---|---|
| PA0–PA7/PC0–PC5 | ADC_IN0–IN15 | 16-channel 12-bit ADC, supports hardware oversampling up to 16 bits (256× sampling), maximum sampling rate 1.14 Msps. |
USART1 (PA9/TX, PA10/RX):
Supports synchronous mode (CK pin, PA8), IrDA infrared communication, LIN master/slave mode, and is compatible with the ISO 7816 smart card protocol.
In Stop mode, it can be woken up by signals with baud rates ≤ 42 Kbaud, suitable for low-power communication scenarios.
LPUART1 (PA2/TX, PA3/RX, PB1/RTS/DE):
Designed for ultra-low power, supports single-wire half-duplex communication. Can operate at 9600 baud in Stop mode using only the LSE clock (32.768 kHz), with wake-up current as low as 0.5 µA.
SPI1 (PA5/SCK, PA6/MISO, PA7/MOSI, PA4/NSS):
Master mode with a maximum speed of 16 Mbit/s, supporting hardware CRC check and SD card protocols. PA15 can be multiplexed as the slave select pin (NSS).
I2C1 (PA9/SCL, PA10/SDA):
Supports Fast Mode Plus (1 Mbit/s) and SMBus/PMBus protocols. Can wake up the chip from Stop mode via address matching and supports multi-slave addressing.
Pin Assignment: PB2 (LPTIM1_OUT), PB5 (LPTIM1_IN1), PB6 (LPTIM1_ETR)
Features:
Independent clock sources (LSE/LSI/HSI/APB), supports operation in Stop mode and can be triggered to wake up by external signals.Pin Assignment:
COMP1: PA0 (INM), PA1 (INP), PA6 (OUT)Features:
Support window comparison mode and can wake up Stop mode. Input voltage range: 0 to VDDA, with typical offset voltage ±3 mV (COMP1).Supported Pins: PA0, PA1, PA2, PB0, PB1, PC13 (6 pins in total)
Function: In Standby mode, a rising edge triggers wakeup with a response time ≤ 50 µs. Can be configured as independent wakeup sources.
VDDA and VSSA:
Analog power and ground must be decoupled independently (recommended: 100 nF ceramic capacitor + 1 µF electrolytic capacitor) to avoid digital noise interfering with ADC/DAC accuracy.VLCD (Pin 6):
Built-in boost converter with a maximum output voltage of 3.6V. Requires an external 0.1–2 µF capacitor for stability, supporting LCD contrast adjustment independent of VDD.| Part | Manufacture | Package / Case | Alternative Instructions | Lifecycle | Overall Risk |
|---|---|---|---|---|---|
| STM32L073RZT6 | STMicroelectronics | LQFP-64 | pin to pin | Mass production | None |
| STM32L073RZT6U | STMicroelectronics | LQFP-64 | pin to pin | Mass production | Medium |
| STM32L073VZT6U | STMicroelectronics | LQFP-100 | pin to pin | Mass production | Medium |
| STM32L083RZT6 | STMicroelectronics | LQFP-64 | pin to pin | Mass production | Low |
| MKM34Z256VLL7 | NXP USA Inc. | LQFP-100 | Functionally similar | Mass production | Low |
| Part number | Manufacturer | Package | Description | |
|---|---|---|---|---|
| STM32L073VZT6 | STMicroelectronics | 100-LQFP | ARM® Cortex®-M0+ STM32L0 Microcontroller IC 32-Bit Single-Core 32MHz 192KB (192K x 8) FLASH 100-LQFP (14x14) | |
| STM32F105VCT7 | Stmicroelectronics | LQFP 100 | This product offers a high-performance solution for 32-bit applications that require robust connectivity features |
| Part number | Manufacturer | Package | Description |
|---|---|---|---|
| STM32L073VZT6 | STMicroelectronics | 100-LQFP | ARM® Cortex®-M0+ STM32L0 Microcontroller IC 32-Bit Single-Core 32MHz 192KB (192K x 8) FLASH 100-LQFP (14x14) |
| STM32C031K6T6 | STMicroelectronics, | LQFP-32 | Compact and cost-effective solution for low-power embedded systems, featuring ARM Cortex-M0+ architecture |