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It is reported that Apple's A17 Bionic chip will use TSMC N3E process next year

Update time : 2023-06-27 15:36:50

On June 24, according to foreign technology media MacRumors, Apple's iPhone 15 Pro and iPhone 15 Pro Max launched this year are equipped with A17 Bionic processors and the A17 version launched next year: the former adopts TSMC N3B process, while the latter adopts Enhanced N3E process.

Compared to the A14, A15 and A16 chips based on the 5nm process, Apple's A17 Bionic this time adopted the 3nm manufacturing process for the first time. It is reported that the A17 Bionic used in the iPhone 15 Pro series adopts the N3B process, and the models launched next year will be fully switched to the N3E process.
According to previous reports, TSMC talked about some data from the 3nm base version (N3B) node and the 3nm enhanced version (N3E). Simply put, the N3E is a slightly "cheaper" version of the N3B, and it can be said that on the final chip, it pays more attention to power control than performance. For the new N3E node, the high-density SRAM bit cell size has not been reduced, and it is still 0.021 µm ², which is exactly the same as the bit cell size of the N5 node.
During the IEDM, TSMC revealed that the N3B has a CGP of 45nm, the densest revealed to date. This is ahead of Intel 4's 50nm CGP, Samsung 4LPP's 54nm CGP, and TSMC N5's 51nm CGP. As the N3B failed to meet TSMC's performance, power, and production goals, the N3E was developed. The aim was to address the shortcomings of the N3B. The first major change was a slight relaxation in metal spacing. Instead of using multiple patterned EUVs on the M0, M1, and M2 metal layers, TSMC retreated and switched to a single patterning.
During IEDM, TSMC revealed that the bit cell size of the N3E was 0.021 μm2, exactly the same as N5. This was a devastating blow to SRAM. Due to yield, TSMC reduced SRAM cell size to N3B.
The N3B implements SRAM scaling, and its cell size is only 0.0199 µm ², a 5% reduction from the previous version. The N3E has a memory density (ISO-assist circuit overhead) of approximately 31.8 Mib/mm ².

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