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Intel Introduces Agilex 7 FPGA with R-Tile, the First FPGA Chip with PCIe 5.0 and CXL Capabilities

Update time : 2023-05-24 10:43:12

Intel's Programmable Solutions Division today announced that Intel Agilex 7 with R-Tile small-chip is shipping in volume. This will bring customers the first FPGA with PCIe 5.0 and CXL capabilities, and the only FPGA product with hard intellectual property supporting these interfaces.

"Customers need cutting-edge technology that offers scalability and customisation to not only manage their current workloads efficiently, but also to adapt capabilities and functionality as their needs evolve. Our Agilex products can provide customers with the speed, power and functional innovation they need, while providing flexibility and resilience for the future. For example, customers are leveraging R-Tile with PCIe Generation 5 and CXL to accelerate software and data analytics, reducing processing times from hours to minutes," said Shannon Poulin, vice president and general manager of Intel's Programmable Solutions Group.
Faced with time, budget and power constraints, organizations across a wide range of industries, including data centres, telecommunications and financial services, are turning to FPGAs as a flexible, programmable and efficient solution. With Agilex 7 and R-Tile, customers can seamlessly connect their FPGAs to processors such as 4th generation Intel Xeon Scalable processors. the configurable and scalable architecture of Agilex 7 enables customers to rapidly deploy custom technology for their specific needs, reduce overall design costs and development processes at massive hardware speeds, and accelerate execution for optimal data centre performance.
Agilex 7 FPGAs with the R-Tile chip have leading technology capabilities compared to other FPGA competitors, with 2x faster PCIe 5.0 bandwidth and 4x higher bandwidth per port CXL.
According to a white paper by Meta and the University of Michigan, adding an FPGA with CXL memory to a 4th generation Xeon-based server, along with efficient page placement using Transparent Page Placement (TPP), can improve Linux performance by 18%.
In addition, UnifabriX demonstrated its CXL-enabled smart memory nodes in several performance benchmarks, one of which showed a 28% improvement in HPCG (High Performance Conjugate Gradient) benchmark scores while utilizing more than 2x the 4th generation Xeon cores to handle HPC workloads.

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