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Intel's new stacked CFET transistor architecture revealed, expected to advance the process to 0.2nm

Update time : 2023-05-25 11:56:30

May 24 news, recently held in Antwerp, Belgium, ITF World 2023 conference, Intel technology development general manager Ann Kelleher introduced several key areas of the latest technological developments, including Intel will use the stacked CFET transistor architecture, which is the first time Intel publicly introduced the new transistor design, but did not mention the specific mass production Timetable.

At the 2021 Innovation Technology Conference, Intel announced the Intel 20A process will use Gate All Around (GAA) technology based RibbonFET transistor architecture to replace the FinFET transistor architecture used in 2011 to date. Ann Kelleher said that RibbonFET will be in mass production in 2024.
Intel is also demonstrating a next-generation GAA stacked CFET transistor architecture that will allow stacking of eight nanosheets, twice the four nanosheets of the RibbonFET, which will further increase transistor density. CFET transistors stack n and p MOS elements together to achieve higher densities. Intel is working on two types of CFET transistors, namely monolithic and sequential, but has not determined which CFET transistor will be used in the end, or if other classes of designs will emerge.
Intel said that with CFET transistor technology, 2032 will be expected to evolve to 5 em (0.5nm), 2036 will be expected to achieve 2 em (0.2nm), CFET transistor architecture type will also change, is also inevitable. However, Intel only outlines the approximate development blueprint of transistor technology, and does not share too many details, the future should also successively disclose more information published.

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